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1 motorola tmos power mosfet transistor device data
? ? "'# % #!$$%"# '% $" % "&!%! " nchannel enhancementmode silicon gate this advanced tmos efet is designed to withstand high energy in the avalanche and commutation modes. the new energy efficient design also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? isolated mounting hole reduces mounting hardware maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 150 vdc draingate voltage (r gs = 1.0 m w ) v dgr 150 vdc gatesource voltage e continuous gatesource voltage e nonrepetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current e continuous drain current e continuous @ 100 c drain current e single pulse (t p 10 m s) i d i d i dm 35 26.9 105 adc apk total power dissipation derate above 25 c p d 180 1.45 watts w/ c operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy e starting t j = 25 c (v dd = 80 vdc, v gs = 10 vdc, i l = 20 apk, l = 3.0 mh, r g = 25 w ) e as 600 mj thermal resistance e junction to case thermal resistance e junction to ambient r q jc r q ja 0.70 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c designer's data for aworst caseo conditions e the designer's data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. efet and designer's are trademarks of motorola, inc. tmos is a registered trademark of motorola, inc. preferred devices are motorola recommended choices for future use and best overall value. rev 3 order this document by mtw35N15E/d
semiconductor technical data ? motorola, inc. 1996 tmos power fet 35 amperes 150 volts r ds(on) = 0.05 ohm case 340k01, style 1 to247ae motorola preferred device ? d s g free datasheet http:///
2 motorola tmos power mosfet transistor device data electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 150 e e 210 e e vdc mv/ c zero gate voltage drain current (v ds = 150 vdc, v gs = 0 vdc) (v ds = 150 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss e e 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 e e 7.0 4.0 e vdc mv/ c static drainsource onresistance (v gs = 10 vdc, i d = 17.5 adc) r ds(on) e e 0.05 ohm drainsource onvoltage (v gs = 10 vdc) (i d = 35 adc) (i d = 17.5 adc, t j = 125 c) v ds(on) e e 1.45 e 1.8 1.7 vdc forward transconductance (v ds = 10 vdc, i d = 17.5 adc) g fs 11 18 e mhos dynamic characteristics input capacitance (v 25 vdc v 0 vdc c iss e 3600 5040 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 855 1170 reverse transfer capacitance f = 1 . 0 mhz) c rss e 165 330 switching characteristics (2) turnon delay time (v 75 vd i 35 ad t d(on) e 28 56 ns rise time (v dd = 75 vdc, i d = 35 adc, v gs =10vdc t r e 170 346 turnoff delay time v gs = 10 vd c, r g = 9.1 w ) t d(off) e 90 180 fall time g ) t f e 103 210 gate charge (see figure 8) (v 120 vd i 35 ad q t e 98 137 nc (see figure 8) (v ds = 120 vdc, i d = 35 adc, q 1 e 19 e ( ds , d , v gs = 10 vdc) q 2 e 49 e q 3 e 40 e sourcedrain diode characteristics forward onvoltage (1) (i s = 35 adc, v gs = 0 vdc) (i s = 35 adc, v gs = 0 vdc, t j = 125 c) v sd e e 0.95 0.9 1.5 e vdc reverse recovery time (see figure 14) (i 35 ad v 0 vd t rr e 200 e ns (see figure 14) (i s = 35 adc, v gs = 0 vdc, t a e 167 e ( s , gs , di s /dt = 100 a/ m s) t b e 32 e reverse recovery stored charge q rr e 1.63 e m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d e 4.5 e nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s e 13 e nh (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature. free datasheet http:///
3 motorola tmos power mosfet transistor device data typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) 0 4.0 10 30 50 70 v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) 2.0 4.0 6.0 8.0 0 10 30 50 70 i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics 05070 0.01 0.03 0.06 0.08 0.09 r ds(on) , drain-to-source resistance (ohms) 05070 0.035 0.039 0.047 i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage 50 0 1.0 2.5 r ds(on) 0 50 150 0.1 10 100 1000 t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage , drain-to-source resistance (normalized) i dss , leakage (na) 25 0 25 50 75 100 125 150 t j = 25 c v ds 10 v 100 c 25 c t j = 100 c 25 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 10 v v gs = 10 v i d = 17.5 a 7.0 v 6.0 v 5.0 v 8.0 v 3.5 2.5 1.5 0.5 5.0 3.0 20 30 40 60 20 60 10 100 40 20 20 40 60 0.05 0.07 0.043 0.5 v gs = 10 v t j = 125 c 100 c 25 c 7.0 9.0 v 2.0 1.0 3.0 60 40 30 0.02 0.04 10 0.041 0.045 0.037 2.0 1.5 0 t j = 55 c 55 c 15 v 1.0 free datasheet http:///
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are deter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculat- ing rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when cal- culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely op- erated into an inductive load; however, snubbing reduces switching losses. space 10 0 10 20 25 gatetosource or draintosource voltage (volts) c, capacitance (pf) figure 7. capacitance variation 10000 6000 4000 2000 0 v gs v ds c oss t j = 25 c v ds = 0 v v gs = 0 v 5515 c rss c rss 8000 c iss free datasheet http:///
5 motorola tmos power mosfet transistor device data draintosource diode characteristics 0.5 0.6 0.7 0.8 0.95 0 5 15 25 35 v sd , sourcetodrain voltage (volts) figure 8. gatetosource and draintosource voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 0 10 100 1000 100 10 t, time (ns) v dd = 75 v i d = 35 a v gs = 10 v t j = 25 c t r t f t d(off) t d(on) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current 120 v gs , gatetosource voltage (volts) 100 60 40 20 0 0 8.0 4.0 0 q t , total charge (nc) v ds , draintosource voltage (volts) 12 6.0 2.0 20 80 100 v gs 40 0.55 0.65 0.75 0.85 10 20 30 v ds q2 q1 q3 60 10 80 qt t j = 25 c i d = 35 a 0.9 safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is for- ward biased. curves are based upon maximum peak junc- tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the offstate and the onstate may tra- verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power aver- aged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reli- able operation, the stored energy from circuit inductance dis- sipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a con- stant. the energy rating decreases nonlinearly with an in- crease of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of drain tosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous cur- rent (i d ), in accordance with industry custom. the energy rat- ing must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at cur- rents below rated continuous i d can safely be assumed to equal the values indicated. free datasheet http:///
6 motorola tmos power mosfet transistor device data safe operating area t j , starting junction temperature ( c) e as , single pulse draintosource figure 11. maximum rated forward biased safe operating area v ds , draintosource voltage (volts) figure 12. maximum avalanche energy versus starting junction temperature 10 1000 avalanche energy (mj) i d , drain current (amps) 1.0 0 25 50 75 100 125 600 300 100 i d = 35 a 500 100 150 t, time (s) figure 13. thermal response r(t), normalized effective transient thermal resistance figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0.2 0.05 0.1 1.0e05 1.0e04 1.0e03 0.01 1.0e02 1.0e01 1.0e+00 1.0e+01 1.0 0.01 1 ms 10 ms dc 0.1 10 m s 200 400 d = 0.05 r ds(on) limit thermal limit package limit 100 m s v gs = 20 v single pulse t c = 25 c r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.02 single pulse 0.1 1000 10 1.0 100 free datasheet http:///
7 motorola tmos power mosfet transistor device data package dimensions case 340k01 issue o style 1: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. r p a k v f d g u l e 0.25 (0.010) m tb m 0.25 (0.010) m yq s j h c 4 123 t b y q dim min max min max inches millimeters a 19.7 20.3 0.776 0.799 b 15.3 15.9 0.602 0.626 c 4.7 5.3 0.185 0.209 d 1.0 1.4 0.039 0.055 e 1.27 ref 0.050 ref f 2.0 2.4 0.079 0.094 g 5.5 bsc 0.216 bsc h 2.2 2.6 0.087 0.102 j 0.4 0.8 0.016 0.031 k 14.2 14.8 0.559 0.583 l 5.5 nom 0.217 nom p 3.7 4.3 0.146 0.169 q 3.55 3.65 0.140 0.144 r 5.0 nom 0.197 nom u 5.5 bsc 0.217 bsc v 3.0 3.4 0.118 0.134 free datasheet http:///
8 motorola tmos power mosfet transistor device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mtw35N15E/d
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